I'm an ECE student who enjoys learning new things, building stuff, and figuring out how things work. Outside academics, I like keeping things simple, exploring new places, and spending time doing things I enjoy.
Expected graduation in 2027.
A few things I enjoy in my free time.
A good way to stay active, competitive, and have fun.
I enjoy exploring new places, experiencing different surroundings, and getting away from the usual routine.
I use Windows only to play games.
Contributed to the FPGA implementation of a 1D CNN-based ECG signal classification system, designing systolic-array multipliers and a MAC unit in Verilog for efficient convolution. Performed RTL-level functional verification of pipelined arithmetic datapaths and control logic through simulation.
Designed and simulated a Class-B RF power amplifier using a 65 nm CMOS PDK, developing an adaptive feedforward bias technique with replica biasing to reduce crossover distortion while maintaining efficiency. Designed and simulated the layout of an on-chip transformer by modifying a PDK inductor.
Verilog · SystemVerilog ↗ · C
Vivado · Quartus Prime · ModelSim · Cadence Virtuoso · VS Code
Designed and implemented a basic RISC-V processor in Verilog based on the RV32I open-source instruction set architecture. Architected the instruction decoder to classify R, I, S, B, U, and J-type instructions and generate control signals for datapath execution. Verified functional correctness through simulation using custom instruction sequences to validate instruction flow and pipeline behaviour.
Developed an autonomous maze-solving robot on FPGA using Verilog and the Trémaux algorithm to compute an optimal navigation path from real-time ultrasonic and IR sensor inputs. Designed a custom UART interface for Bluetooth communication, integrated ultrasonic, DHT, and soil-moisture sensors, and implemented PWM-based motor control entirely in Verilog. Verified RTL functionality through simulation and on-board FPGA debugging.
Designed and implemented a parameterized asynchronous FIFO in Verilog for safe data transfer between independent clock domains. Used Gray-coded read/write pointers and double flip-flop synchronizers to mitigate metastability and ensure reliable clock-domain crossing, with robust full and empty flag logic to manage FIFO status.